This application claims the priority of Korean Patent Application No. 2002-54605 filed on Sep. 10, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having metal interconnections of different thicknesses using a damascene process.
2. Description of the Related Art
In a general method of manufacturing a semiconductor device, active elements and/or passive elements are formed on a semiconductor substrate, and then metal interconnections are formed over the active elements and/or passive elements. As integration densities of semiconductor devices increase, the metal interconnections have begun to be formed in a multilayer configuration. Insulating layers are interposed between the multilayered metal interconnections, and the multilayered metal interconnections are electrically connected by a via-contact through the insulating layers.
In the semiconductor device including the multilayered metal interconnections, many problems due to electric coupling between the adjacent metal interconnections occurs. Among many problems, a typical problem greatly affecting the operation speed of the semiconductor device is RC delay. Since the operation speed of the semiconductor device becomes slower as the RC delay becomes larger, it is preferable to reduce the RC delay.
Factors that affect the RC delay are resistances of the metal interconnections and capacitances of the insulating layers interposed between the metal interconnections. Resistivities of materials of the metal interconnections, widths of the metal interconnections, lengths of the metal interconnections, and the like, are variables that can affect the resistances of the metal interconnections. Dielectric constants of materials of the insulating layers, thicknesses of the insulating layers, and the like, are variables that can affect the capacitances of the insulating layers.
However, a semiconductor device may include a region where the capacitances of the insulating layers interposed between the metal interconnections are a dominant cause of RC delay and a region where the resistances of the metal interconnections are a dominant cause of the RC delay. Therefore, in a case where the factors affecting the RC delay differ locally, the RC delay must be minimized by adjusting the factors affecting the RC delay locally, i.e., according to the regions. For example, the RC delay can be minimized in a region where the capacitances of the insulating layers are the dominant cause of the RC delay by increasing the thicknesses of the insulating layers, and in this respect, the thicknesses of the metal interconnections are necessarily decreased. In contrast, the RC delay can be minimized in the region where the resistances of the metal interconnections are the dominant cause of the RC delay by increasing the thicknesses of the metal interconnections, and in this respect, the thicknesses of the insulating layers are necessarily decreased. Thus, in order to minimize the RC delay, it is desirable to differ the thicknesses of the metal interconnections in a single process, in order to have an efficient device fabrication process.